Advanced packaging means combining dies and SMT components into system-in-package (SiP) applications, embedding them in substrate cavities (embedded PCB), or the contacts of dies spreading out the contacts of dies via wafer-level-fan-out (WLFO) or panel-level-fan-out (PLFO) processes. The goal is to pack more functions into an ever-smaller space with the fastest time to market.
As the demand increases for increasingly smaller IoT devices, sensors, power modules and medical devices, more manufacturers and industries are discovering the potential of this technology – and subsequently want more performance and productivity from their manufacturing equipment. This is where we at ASMPT come into play with our portfolio of advanced packaging solutions.
New applications in electronics drive advances in miniaturization, component density and modularization while the pressure on costs keeps rising. In response, semiconductor makers and contract manufacturers resort more and more to advanced packaging technologies like fan-out wafer level and fan-out panel level packaging (FOWL/FOPLP), these formats are increasingly combined with 3D and SiP technologies. This permits them to develop microelectronics with more functional density as well as outstanding electrical and thermal properties. Advanced packaging technologies are extremely complex and demand manufacturing methods with exceptional precision in all process steps. Close control and optimization of all parameters ensure that quality and yield rates can be brought up to the required levels even in high volume environments. The only way to accomplish this is with manufacturing equipment that‘s equally precise and efficient.
"Data is the new oil" so they say and thus there are new demands on electronics for data collection, communication, and analysis. The basis for the communication lies in the 5G mobile data network that is currently under construction, and the many devices must have powerful and highly miniaturized communication modules installed.
This degree of integration is achieved by combining many heterogeneous active and passive components into an SiP (system-in-a-package) with technologies like active embedding or multi-layered, three-dimensional structures. To enable this process ASMPT offers a wide range of different die & flip chip bonders to meet any of your packaging requirements: From Highest Speed Chip and SMD placement, like the SIPLACE TX micron, sub-micron die bonding, like the AMICRA NANO or even precise die & flip chip bonders.
Miniaturization and modularization, two major trends in Semiconductor packaging continues to be the main driving force to meet the need of a new generation of devices stemming from the introduction of 5G, Internet of Things, and other mobile devices. Advanced packaging technologies, such as embedded dies, which can be processed in large panels that incorporates embedded devices - both passives and active dies, have emerged as the solution to meet the requirement for greater flexibility, faster time to market, and lower costs.
SIPLACE CA (Chip Assembly) is the solution that can handle large, thin substrates and place large number of different types of dies and passives into confined spaces to meet the expected growth for modules, and the drive for higher performance and increasing functionality within thinner form factors in embedded SIP solutions.
In the past, the semiconductor – especially in back-end packaging operations – and SMT production industries operated separately from each other. In advanced packaging, their processes overlap for the first time. The result: Besides OSATs, classic electronics manufacturers can help out the semiconductor industry by supplementing its operations to meet the exploding demand for ultra-compact, SMT capable function modules. This opens up an attractive growth market for the electronics production industry.
A placement solution like the SIPLACE CA (Chip Assembly) can fan-out packages that combines bare dies with SMT components to form compact SiPs (systems-in-package) at wafer level and also panel-level.
In addition to die & flip-chip bonding, ASMPT also offers a complete process solution for wafer-level package assembly - from chip placement to component inspection, sorting and taping.
More functionalities requires more power and frequently changing loads and high temperatures cause conductive connections in power electronics to age quickly. One solution to this problem involves temperature-resistant materials such as nano-silver pastes.
The solution: With silver sintering, nano-silver particles can be shaped to form stable connections without melting. The DEK Galaxy can easily deposit silver paste and when combined with other ASMPT solutions for Silver sintering, die-attach and wire bonding, component manufacturers can produce more durable IGBTs with improved electrical and thermal properties.
The rising spread of mobile devices and the Internet of Things (IoT) push the need for ever smaller modules and components. Electronics must be increasingly integrated and produced in accordance with the highest quality standards, but at ever lower cost.
One response to these challenges is advanced packaging, which integrates bare dies or flip-chips with SMT components to form ultra-compact systems (system-in-package, or SiP). Advanced packaging techniques make it possible to create complete function modules that can then be placed efficiently and reliably on an SMT line.