Unlocking Next-Gen Wafer Processing: ASMPT ALSI's Innovative Multi-Beam Technology

As silicon (Si) wafers become thinner and the thickness of active layers and Back Side Metallization (BSM) increases, manufacturers in hybrid bonding and the memory industry seek innovative ways to process their materials.

With metal test structures and test element groups (TEG) present in wafer streets, removing the top layer of the wafer is crucial for enabling next-generation applications.

ASMPT ALSI unique multi-beam technology, utilizing patented Matrix-DOE’s, provides a fully optimized process and outstanding customer value by:

• Achieving low Heat Affected Zone (HAZ)
• Achieving very low to zero burr
• Ensuring a smooth bottom and steep sidewalls

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