Die-to-wafer hybrid bonding is a pivotal process for enabling the redesign of system-on-chip (SoC) devices to 3D stacked chips via chiplet technology—combining chips with different process nodes into advanced packaging systems that can power new applications such as 5G, high performance computing (HPC) and artificial intelligence (AI).
ASMPT's next evolution of IC interconnect solutions — LITHOBOLT™ — Hybrid bonder for Die-to-Wafer hybrid bonding, will complement our total interconnect solutions for heterogeneous integration.
Brochure
Complete portfolio for wafer level and panel level packaging technologies.