ASMPT Semiconductor Solutions
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  • Advanced Packaging
  • CMOS Image Sensor
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Advanced Packaging

Advanced packaging means combining dies and SMT components into system-in-package (SiP) applications, embedding them in substrate cavities (embedded PCB), or the contacts of dies spreading out the contacts of dies via wafer-level-fan-out (WLFO) or panel-level-fan-out (PLFO) processes. The goal is to pack more functions into an ever-smaller space with the fastest time to market.

As the demand increases for increasingly smaller IoT devices, sensors, power modules and medical devices, more manufacturers and industries are discovering the potential of this technology – and subsequently want more performance and productivity from their manufacturing equipment. This is where we at ASMPT come into play with our portfolio of advanced packaging solutions.

Deposition Solutions

PVD Wafer ECD Wafer ECD Panel

Laser Dicing & Grooving

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Fan-out

In the past, the semiconductor – especially in back-end packaging operations – and SMT production industries operated separately from each other. In advanced packaging, their processes overlap for the first time. The result: Besides OSATs, classic electronics manufacturers can help out the semiconductor industry by supplementing its operations to meet the exploding demand for ultra-compact, SMT capable function modules. This opens up an attractive growth market for the electronics production industry.

A placement solution like the SIPLACE CA (Chip Assembly) can fan-out packages that combines bare dies with SMT components to form compact SiPs (systems-in-package) at wafer level and also panel-level.

ASMPT offers NUCLEUS series for die & flip-chip bonding, and the complete process solution for wafer-level package assembly - from chip placement to component inspection, sorting and taping.

Thermocompression Bonding

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Hybrid Bonding

  • Chip-to-Wafer hybrid bonding
  • Interconnect solutions for heterogeneous integration

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Inspection, Test & Packing

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