Deposition Solutions

Bumping is an advanced wafer level process technology where “bumps” or “balls” made of various metals are formed on the substrate before the wafer or board is cut, or “diced” into individual chips. Wafer bumping is an essential part of flip chip or board level semiconductor packaging which has become the standard in interconnect technology in consumer electronics today. These “bumps” are the components that connect the die to the substrate and become the package after singulation. These interconnect building blocks can be bumps or copper pillars, composed of metal solders, such as eutectic or lead free SnAg.

The bumps, or pillars, provide shorter pathways than wire bonds between die and substrate to improve the electrical, mechanical and thermal performance of the flip chip package. For the performance driven market, flip chip interconnects reduce signal propagation delay, provide better bandwidths, and relieve the constraints of power distribution. Bump composition and dimension depends on requirements such as final form factor, cost and the electrical, mechanical and thermal performance. Cu Pillar structures have become the interconnect solution of choice for fine pitch, lead-free, or high current application devices. For the form factor driven market, such as mobile applications, replacing wire bonding by flip chip interconnects reduces the size and weight of the package as well as delivering better performance.

Cu Pillar	Bumps	RDL	Via Fill

The Fan Out process generally represents the redistribution of the interconnects located inside and outside of the die envelope. The term fan out often includes a variety of assembly methods: embedded wafer level package (WLP), embedded wafer level ball grid array (eWLB), wafer level system in package (WLSiP). The Fan Out process can also embed chip capacitors and inductors and has also been contemplated for 3D die stacking.

The Fan Out technology is often a process of reconstituting a new wafer or panel on all KGD (known good die). KGD are accurately placed and temporarily held on to an interposer with double-sided sticky tape or an adhesive. Then, EMC (Embedded Mold Compound) is applied to create a new wafer or panel. Once the new wafer or panel is created, then the front-end lithography steppers apply the RDL (Redistribution Layer) connecting and relocating the interconnections. The RDL process demands that increasingly thin PVD seeds be sputtered and finer RDLs be plated with micron accuracy and tight uniformity over the entire wafer or panel substrate. One of the major challenges is finding sputtering and plating machines that can deliver thin, uniform seeds and fine line RDL plating below 10 µm L/S uniformly across a variety of large areas.

Cu Pillar	Bumps	RDL	Marco Cu Pillar